The present invention relates generally to semiconductor memory devices and, in particular, to redundant output switches for use in a semiconductor memory device.
Many of today""s semiconductor memory devices include redundant elements that are available to replace malfunctioning or defective elements. By including redundant elements on memory devices, the overall yield of marnfacture can be increased and improved. Therefore, the use of redundant elements on a memory chip to replace defective elements can result in lower capital manufacturing costs and earlier introduction of new products on existing wafer fab lines or in new process technologies.
As illustrated in FIG. 1, a conventional semiconductor memory device includes an ordinary memory cell array 11, an ordinary decoder 12, a redundant switch circuit 13 and a redundant memory cell array 14. Typically, the ordinary memory cell array 11 has a plurality of ordinary memory cells 11 (m,n) arranged in an M-column-by-N-row structure, where 1xe2x89xa6mxe2x89xa6M, 1xe2x89xa6nxe2x89xa6N and M, N are a first and a second positive integers greater than one. That is, the ordinary memory cell array 11 includes M columns, and each column has N ordinary memory cells. In other words, the ordinary memory cell array 11 includes N rows, and each row has M ordinary memory cells.
The memory cell array 11 also comprises 1st through Mth bit lines or ordinary columns 11B-1 to 11B-M, and 1st through Nth word lines 11W-1 to 11W-N. Arn ordinary memory cell refers to 11 (m,n) that is connected to the mth bit line 11B-m and the nth word line 11W-n. As depicted in FIG. 1, the ordinary memory cell array 11 is coupled to a data bus 102. The ordinary memory cell array 11 is also connected to the ordinary decoder 12. The decoder 12 receives an address signal and its complement from an address bus 101. When a decode-inhibit signal 106 is de-asserted, the ordinary decoder 12 decodes the received pair of complementary address signals to generate a column and a row decode signals 104C, 104R and to provide them to the ordinary memory cell array 11.
The ordinary decoder 12 includes a row decoder 12R and a column decoder 12C. The row decoder 12R receives a row address and its complement. The decoder 12R decodes the pair of complementary row addresses to generate the row decode signal 104R. In similar fashion, the column decoder 12C receives a column address and its complement. The decoder 12C decodes the pair of complementary column addresses to generate the column decode signal 104C. The row decode signal 104R is provided for driving one of the N word lines. Lkewise, the column decode signal 104C is provided for driving one of the M bit lines.
Still referring to FIG. 1, the redundant memory cell array 14 has a plurality of redundant memory cells 14 (p,n) arranged in a P-column-by-N-row structure, where 1xe2x89xa6pxe2x89xa6P, 1xe2x89xa6nxe2x89xa6N and P is a third positive integer greater than one. That is, the redundant memory cell array 14 includes P columns, and each column has N redundant memory cells. In other words, the redundant memory cell array 14 includes N rows, and each row has P redundant memory cells.
The redundant memory cell array 14 also comprises 1st through Pth bit lines or redundant columns 14B-1 to 14B-P, and 1st through Nth word lines 14W-1 to 14W-N. A redundant memory cell refers to 14 (p,n) that is connected to the pth bit line 14B-p and the nth word line 14W-n. The redundant switch circuit 13 is coupled between the redundant memory cell array 14 and the data bus 102 as shown in FIG. 1.
The semiconductor memory device is tested shortly after it is manufactured to find and identify ordinary columns that contain defective ordinary memory cells. If one or more defective columns are identified, they are replaced with redundant columns of the redundant memory cell array 14 such that the memory device having defective cells is still an acceptable product.
A defective column address for the ordinary memory cell array 11 is set by cutting isolation elements, such as fuses, in a redundant decoder 15. When a defective column is addressed, the redundant decoder 15 and the redundant switch circuit 13 operate in a manner that is transparent to the external circuitry thereby routing all data transactions to the corresponding redundant column instead of the defective column in the ordinary memory cell array 11.
Referring to FIG. 2, the redundant decoder 15 includes P redundant decode circuits 15-1xcx9c15-P that are each connected to a corresponding redundant column in the redundant memory cell array 14. As an illustrated example, the third positive integer P is equal to 2. Hence, the redundant decoder 15 has redundant decode circuits 15-1 and 15-2. Since the redundant decode circuits 15-1 and 15-2 are constructed and operate in a similar fashion, the detailed schematic diagram of the redundant decode circuit 15-2 is omitted in FIG. 2.
For illustration, the memory device described herein provides an 8-bit column address [X1T:X8T] and an 8-bit complementary column address [X1N:X8N]. Typically, a semiconductor memory device provides Q-bit column address and Q-bit complementary column address separately, where Q is a fourth positive integer greater than one. As depicted, the redundant decode circuit 15-1 includes sixteen NMOS transistors 201xcx9c2016, a PMOS transistor 21, sixteen fuses 221xcx9c2216, and an AND gate 206.
The PMOS transistor 21 has its source connected to a high voltage source, its drain connected to a common node 201, and its gate connected to a control circuit (not shown) to receive a control signal 103a. The fuses 221xcx9c2216 are coupled between each of the NMOS transistors 201xcx9c2016 and the common node 201. Each NMOS transistor (201xcx9c2016) has its source connected to ground or a low voltage source, and its drain connected to the corresponding fuse (221xcx9c2216) The odd numbered NMOS transistors 201, 203, . . . , 2015 have their gates receive the 8-bit column address [X1T:X8T] of the address signal; the even numbered NMOS transistors 202, 204, . . . , 2016 have their gates receive the 8-bit complementary column address [X1N;X8N] of the address signal.
One input terminal of the AND gate 206 is connected to the conmon node 201, the other input terminal of the AND gate 206 is connected to the control circuit (not shown) to receive a control signal 103b. The AND gate 206 generates a redundant decode signal 105-1 and provides it to the 1st redundant column in the redundant memory cell array 14 in FIG. 1. In similar fashion, the redundant decode circuit 15-2 receives the column address [X1T:X8T] and its complement [X1N:X8N], and the control signals 103axcx9cb. Therefore, the redundant decode circuit 15-2 generates a redundant decode signal 105-2 and provides it to the 2nd redundant column in the redundant memory cell array 14 in FIG. 1. The redundant decoder 15 further includes an OR gate 203 receiving the redundant decode signals 105-1 and 105-2. The OR gate asserts the decode-inhibit signal 106 when the redundant decode signal 105-1 or 105-2 is activated.
Referring now to FIG. 3, the redundant switch circuit 13 comprises output set circuits 130-1 and 130-2 respectively receiving the redundant decode signals 105-1 and 105-2. Each output set circuit outputs a select code S-1/S-2 according to its internal setting. As illustrated in FIG. 4, each of the output set circuits 130-1 and 130-2 is constructed of PMOS transistors and fuses f-1xcx9cf-M (M=8, for example). By selectively cutting the fuses f-1xcx9cf-8, the pth output set circuit generates output signals [op1:op8] to form the select code S-p. For instance, each output select circuit 132-p is constructed of M switch devices 501xcx9c50M (M=8) as shown in FIG. 5. Each of the switch devices 501xcx9c50M has its input terminal coupled to the pth redundant column 14B-p, and has its output terminal coupled to the corresponding data line of the data bus 102. Whether the switch devices 501xcx9c50M are made conductive or not, depending on the select code S-p, e.g., the output signals [op1:op8].
If two ordinary columns 11B-2 and 11B-B are found to be defective in the ordinary memory cell array 11, the redundant columns 14B-1 and 14B-2 in the redundant memory cell array 14 are mapped to replace the defective columns. The redundant decode circuits 15-1, 15-2 are programmed by selectively blowing fuses (221xcx9c2216) so as to cut the connections required in order to register column addresses of the defective columns 11B-2 and 11B-8.
The external circuitry (not shown) is in communication with the ordinary column 11B-2 by way of a data line 102-2 of the data bus 102. Thus, the redundant column 14B-1 is required to couple to the data line 102-2 by way of the redundant switch circuit 13. All the fuses in the output set circuit 130-1 are cut except the 2nd fuse f-2 as illustrated in FIG. 4. When the defective column 11B-2 is addressed, the redundant decode signal 105-1 of the redurdant decoder 15 is logic xe2x80x9c1xe2x80x9d (as noted, the redundant decode signal 105-2 is logic xe2x80x9cOxe2x80x9d). Therefore, the output set circuit 130-1 generates the select code S-1 equal to xe2x80x9c10111111xe2x80x9d. With reference to FIG. 5, the switch device 502 of the output select circuit 132-1 is made conductive according to the select code S-1, e.g., [op1:op8]=xe2x80x9c10111111xe2x80x9d. As a result, the data line 102-2 is coupled to the redundant column 14B-1 instead of the defective column 11B-2.
In a similar manner, the external circuitry (not shown) is in communication with the ordinary column 11B-8 by way of a data line 102-8 of the data bus 102. Hence, the redundant column 14B-2 is required to couple to the data line 102-8 by way of the redundant switch circuit 13. As illustrated in FIG. 4, all the fuses in the output set circuit 130-2 are blown except the 8th fuse f-8. When the defective column 11B-8 is addressed, the redundant decode signal 105-2 of the redundant decoder 15 is logic xe2x80x9c1xe2x80x9d (as noted, the redundant decode signal 105-1 is logic xe2x80x9c0xe2x80x9d) Thus, the output set circuit 130-2 generates the select code S-2 equal to xe2x80x9c11111110xe2x80x9d. Referring to FIG. 5, the switch device 508 of the output select circuit 132-2 is made conductive according to the select code S-2, e.g., [op1:op8]=xe2x80x9c11111110xe2x80x9d. Consequently, the data line 102-8 is coupled to the redundant column 14B-2 instead of the defective column 11B-8.
One problem with the implementation of the redundant switch circuit 13 according to the prior art is the chance of error during the cutting of the fuses in the output set circuits. For example, if the fuses f-1xcx9cf-8 in the output set circuit 130-p are blown incompletely, the output set circuit 130-p therefore generates an incorrect select code S-p. The incomplete cutting of the fuses can adversely affect the selective connection of the output select circuit 132-p. As a result, a neighborhood interference fault between the data lines 102-1xcx9c102-M is said to occur. Only special test patterns can screen for neighborhood interference faults. Unfortunately, even so, the special test patterns generally provide a partial solution to effective screen for such a failure mode.
Accordingly, what is needed is a novel redundant switch circuit that lowers the chance of incomplete cutting by reducing the total number of fuses. Further, it is desired to provide a semiconductor memory device incorporating the novel redundant switch circuit to improve the overall manufacture yield by preventing data lines from a neighborhood interference fault.
In accordance with one aspect of the invention, a semiconductor memory device includes an ordinary memory cell array and an ordinary decoder. The ordinary memory cell array, arranged in an M-column-by-N-row structure, includes M ordinary columns each of which has N ordinary memory cells, where M and N are a first and a second positive integers greater than one. Each ordinary column is respectively coupled to a corresponding data line of a data bus. The ordinary decoder is connected to the ordinary memory cell array. The ordinary decoder receives a decode-inhibit signal and an address signal, which is provided for decoding the address signal to drive one of the ordinary memory cells when the decode-inhibit signal is de-asserted. The memory device also includes a redundant memory cell array, a redundant decoder and a redundant switch circuit. The redundant memory cell array, arranged in a P-column-by-N-row structure, includes P redundant columns each having N redundant memory cells. The P redundant columns are adapted to replace defective columns in the M ordinary columns, where P is a third positive integer greater than one. If an mth ordinary column is identified as defective and it is replaced with a pth redundant column, the defective column is denoted as Xm-p where 1xe2x89xa6mxe2x89xa6M and 1xe2x89xa6pxe2x89xa6P. The redundant decoder is connected to the redundant memory cell array and the ordinary decoder, which includes P redundant decode circuits respectively receiving a column address of the address signal. In the P redundant decode circuits, a pth redundant decode circuit provides a pth redundant decode signal to the pth redundant column in the redundant memory cell array. The pth redundant decode circuit is employed to drive the pth redundant column when the pth redundant decode circuit receives the column address indicative of the defective column Xm-p. In addition, the redundant switch circuit has P redundant output switches. In response to the pth redundant decode signal and a pth select code, a pth redundant output switch in the P redundant output switches couples the pth redundant column to a mth data line of the data bus corresponding to the defective column Xm-p. The pth select code is generated by selectively cutting k fuses in the pth redundant output switch and where kxe2x89xa6Mxe2x89xa62k.
In accordance with another aspect of the invention, a redundant output switch is provided for use in a semiconductor memory device that has an ordinary memory cell array and a redundant memory cell array. The redundant output switch allows an ordinary column in the ordinary memory cell array to be replaced with a redundant column in the redundant memory cell array if the ordinary column is identified as a defective column. The switch redundant output includes an output set circuit having a plurality of fuses. The output set circuit sets a select code by selectively cutting the fuses. The switch redundant output also includes an output select circuit having an input terminal coupled to the redundant columns and a plurality of output terminals respectively coupled to a plurality of corresponding ordinary columns in the ordinary memory cell array. When the output select circuit receives the select code, it selectively couples the redundant column to the defective column.